The present invention relates to a non-volatile semiconductor memory and, more particularly, a multi-level NAND EEPROM in which data of 2 bits (4-level) or more multi-bits can be stored.
EEPROM, which is one type of non-volatile semiconductor memory, comprises a floating gate electrode (charge storage layer) and a control gate electrode, and the data value stored in the respective memory cell thereof is determined depending on the charge amount in the floating gate electrode.
Normally, in one memory cell, 1-bit (2-level) data xe2x80x9c0xe2x80x9d, xe2x80x9c1xe2x80x9d is stored, but there has recently been developed a multi-level NAND EEPROM which can store therein data of 2 bits (4-level) or more multi-bits can be stored in each memory cell thereof.
FIG. 1 shows the essential portion of a 4-level NAND type flash EEPROM.
Here, it is added that this EEPROM is disclosed in the specification of Japanese Patent Application No. 9-124493 (filed on May 14, 1997).
A memory cell array 1 comprises a plurality of memory cells disposed in the shape of a matrix. These memory cells are constituted in such a manner that the data therein can be electrically rewritten. Further, in the memory cell array 1, there are disposed a plurality of word lines (control gate electrodes), a plurality of bit lines and a source line connected in common to the sources of a plurality of (or all) memory cells.
Further, disposed close to the memory cell array 1 are a bit line control circuit 2 which controls the potential of the bit lines, etc. and a word line control circuit 6 which controls the potential of the word lines, etc.
The bit line control circuit 2 is provided, for instance, for outputting the data in memory cells in the memory cell array 1 to the outside of the chip via the bit line at the time of read, for detecting the state of memory cells in the memory cell array 1 at the time of verify, and for applying a program control voltage to memory cells in the memory cell array 1 at the time of program.
The bit line control circuit 2 includes a plurality of data latch circuits which can hold data corresponding to one page of the memory cell array 1; and, by performing a read operation a plurality of times, the data corresponding to one page can be held at the same time in a plurality of data latch circuits. At the time of read, a column decoder 3 selects the plurality of data latch circuits one by one successively, so that the data corresponding to one page held in the plurality of data latch circuits is outputted serially outward the chip from a data input/output terminal 5 via a data input/output buffer 4.
Further, at the time of program, the column decoder 3 selects the plurality of data latch circuits successively one by one, so that data corresponding to one page is serially inputted from the outside of the chip to the inside thereof and held in the plurality of data latch circuits in the bit line control circuit 2. The data corresponding to one page which is thus held in the plurality of data latch circuits is programmed at the same time into the plurality of memory cells in the memory cell array 1.
In case of an n-bit type memory, such processing operations as mentioned above are performed in n blocks at the same time.
The word line control circuit 6 selects one of the word lines in the memory cell array 1 and applies predetermined potentials corresponding to the read, program and erase modes to the one word line thus selected (selected word line) and the other word lines (non-selected word lines).
The memory cell array 1, the bit line control circuit 2, the column decoder 3, the data input/output buffer 4 and the word line control circuit 6 are controlled by a control signal and control voltage generation circuit 7.
In the 4-level NAND flash EEPROM constituted as mentioned above, the data value stored in the respective memory cell is determined by the amount of electric charges in the floating gate electrode.
More specifically, the state in which the amount of charges in the floating gate electrode is zero is referred to as a neutral state, and the state in which the floating gate electrode stores therein charges which are positive with reference to the neutral state is referred to as an erase state. Further, the erase state is made to correspond to data xe2x80x9c0xe2x80x9d. For example, the erase operation can be executed by applying a high potential (about 20V) to the substrate and the earth potential (0V) to the control gate electrode.
The program state is referred to a state in which the floating gate electrode stores therein charges negative with reference to the neutral state thereof and made to correspond to data xe2x80x9c1xe2x80x9d, xe2x80x9c2xe2x80x9d and xe2x80x9c3xe2x80x9d. However, the amount of charges in the floating gate electrode in its data xe2x80x9c2xe2x80x9d state is set so as to be larger than the amount of charges in the floating gate electrode in its data xe2x80x9c1xe2x80x9d state, and the amount of charges in the floating gate electrode in its data xe2x80x9c3xe2x80x9d state is set so as to be larger than the amount of charges in the floating gate electrode in its data xe2x80x9c2xe2x80x9d state.
For example, the program operation can be executed by setting the substrate, the source and the drain to the earth potential (0V), respectively, and applying a high potential (about 20V) to the control gate electrode.
The structure of the memory cells in the multi-level NAND EEPROM is substantially identical with the structure of the memory cells in a general NAND EEPROM, so that, in case of the multi-level NAND EEPROM in which the data amount storable in one memory cell is larger, the memory capacity of data can naturally be increased as compared with the general NAND EEPROM in which one bit data is stored in one memory cell.
However, generally in case data of 2 or more bits is stored in one memory cell, the reliability of the data lowers in proportion as the rewrite number is increased, with reference to the case where data of one bit is stored in one memory cell.
Therefore, it is very convenient to the user side if 1-bit (2-level) data can be stored in the memory cells in the memory cell array or data of 2 bits (4-level) or more bits can be stored in the memory cells in the memory cell array in accordance with the purpose in use.
Further, in case of the NAND type flash EEPROM, the memory cell array is constituted of a main area, a spare area for storing redundant bits, and a redundancy area for relieving the defective bits in the main area or the spare area.
Here is the demand that, as for the main area and the redundancy area, data of 2 bits (4-level) ore more bits should desirably be stored in one memory cell in order to increase the memory capacity, and, as for the spare area, data of one bit (2-levels) should desirably be stored in one memory cell in order to prevent the reliability of the data from being lowered even if the rewrite number is increased.
It is the object of the present invention to provide a non-volatile semiconductor memory having a switching function to ensure that, as the data stored in one memory cell array, data of 2 bits (4-levels) or more multi-bits (more multi-levels) can be used or data of 1 bit (2-levels) can be used.
The non-volatile semiconductor memory according to the present invention comprises a memory cell array including memory cells arranged in a matrix form a memory cell selecting means for selecting the memory cells read or programmed simultaneously, a plurality of data latch circuits provided corresponding to memory cells selected by the memory cell selecting means, a means constituted in such a manner that the plurality of data latch circuits are grouped by m (m being 2 or a greater natural number) into sets, so that, when data comprising a plurality of bits is read from or programmed into each of the plurality of select memory cells, the means selects one data latch circuit, and, when one-bit data is read from or programmed into each of the plurality of select memory cells, the means selects m data latch circuits in one set, data input/output terminals for the transmission and reception of data to and from the selected one or m data latch circuits.
The above-mentioned means selects one data latch circuit when m-bit data is to be read from or programmed into each of the plurality of select memory cells.
The non-volatile semiconductor memory according to the present invention further comprises a means which, at the time of read, selects the plurality of data latch circuits one by one or m by m successively after the means has made the data in the plurality of select memory to be latched at the same time into the plurality of data latch circuits.
The non-volatile semiconductor memory according to the present invention further comprises a means which, at the time of program, selects the plurality of data latch circuits one by one or m by m to have the data latched in the plurality of data latch circuits and then programs the data of the plurality of data latch circuits into the plurality of select memory cells at the same time.
The plurality of data latch circuits are each connected to at least one bit line and has m sub-data circuits which can latch 1-bit data.
At the time of read or program, the plurality of data latch circuits are each electrically connected to one bit line.
The plurality of data latch circuits are disposed adjacent to one end in the column direction of the memory cell array, and a plurality of data latch circuits which are of the same structure as that of the first-mentioned plurality of data latch circuits are disposed adjacent to the other end in the column direction of the memory cell array.
In case the data comprising a plurality of bits is read from or programmed into a portion of the plurality of select memory cells, and 1-bit data is read from or programmed into the other portion of the plurality of select memory cells, the means selects one data latch circuit when the data comprising a plurality of bits is read from or programmed into a portion of the plurality of select memory cells, and the means selects m data latch circuits in one set when 1-bit data is read from or programmed into the other portion of the plurality of select memory cells.
A portion of the plurality of select memory cells exists in the main area in which normal bits are stored, and the other portion of the plurality of select memory cells exists in the spare area in which redundant bits are stored.
The memory cell array has a redundancy area and, in case a portion of the plurality of select memory cells is replaced with the memory cells in the redundancy area, the plurality-of-bit data is read from or programmed into the memory cells in the redundancy area, and, in case the other portion of the plurality of select memory cells are replaced with the memory cells in the redundancy area, the 1-bit data is read from or programmed into the memory cells in the redundancy area.
In case m is 2, the plurality of data latch circuits are connected to the data input/output buffer through first, second and third data lines, and, when the 2-bit data is read from or programmed into a portion of the plurality of select memory cells, the first and second data lines or the first and third data lines are used, and, when the 1-bit data is read from or programmed into the other portion of the plurality of select memory cells, the second and third data lines are used.
The plurality of data latch circuits each comprise two sub-data circuits which each can latch 1-bit data, the first data line is connected to first sub-data circuits of the plurality of data latch circuits, the second data line is connected to the second sub-data circuits in a predetermined number of data latch circuits, the third data line is connected to the second sub-data circuits in the data latch circuits excepting the predetermined number of data latch circuits.
In case the above-mentioned m is 2, the plurality of data latch circuits are connected to a data input/output buffer through first to fourth data lines, and, when 2-bit data is read from or programmed into a portion of the plurality of select memory cells, the first and second data lines or the third and fourth data lines are used, and, when 1-bit data is read from or programmed into the other portion of the plurality of select memory cells, the first and third data lines or the second and fourth data lines are used.
The plurality of data latch circuits each comprise two sub-data circuits which each can latch 1-bit data, and the first data line is connected to first sub-data circuits in a predetermined number of data latch circuits, the second data line is connected to the second sub-data circuits in the predetermined number of data latch circuits, the third data line is connected to the first sub-data circuits in the data latch circuits excepting the predetermined number of data latch circuits, and the fourth data line is connected to the second sub-data circuits in the data latch circuits excepting the predetermined number of data latch circuits.
The non-volatile semiconductor memory is of the type that plurality-of-bit data is stored in one memory cell and comprises a means which, at the time of read, achieves the read of data from the above-mentioned one memory cell by a plurality of continuous read operations, and a means which, at the time of test, executes the plurality of read operations separately from one another to confirm whether the respective operations are normal or not.
The non-volatile semiconductor memory according to the present invention comprises a means which, at the time of program, achieves the program of data into memory cells by repeating a program operation and a verify operation, and a means which always renders the data in all the memory cells to xe2x80x9c0xe2x80x9d or compulsorily renders, into a fail state, a flag showing the result of a verify into a fail state, and makes the program operation and the verify operation to be performed repeatedly up to the maximum loop count.
The non-volatile semiconductor memory according to the present invention further comprises a means which, at the time of test, repeatedly performs the program operation and the verify operation up to the maximum loop count to thereby perform a stress test.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.